1. Field of the Invention
The present invention generally relates to a semiconductor memory device, and more particularly to a layout of a line for shielding a data bus from a column selection line in a semiconductor memory device.
2. Description of the Related Art
FIG. 1 shows a block diagram of a conventional synchronous dynamic random access memory (SDRAM) which is one type of dynamic random access memories. An SDRAM 100 mainly includes a command decoder 101, a column control circuit 102, a row control circuit 103 and memory banks 118-1 to 118-N. Each of the memory banks 118-1 to 118-N has a row address buffer 104, a row-decoder 105, a memory cell array 106, a column address buffer 107, a column-decoder 108, a sense amplifier block 109, the read/write amplifier block 120 which includes the read amplifier block 110 and the write amplifier block 111 and the input/output control circuit 112. A clock signal CLK, a row address strobe signal RAS, a column address strobe signal CAS, a write enable signal WE, a chip selection signal CS, a clock enable signal CKE and address signals A0 to A15 are supplied to the SDRAM 100 and data DQ is input to or output from the SDRAM 100 based on the signals. The command decoder 101 and the input/output control circuit 112 in the SDRAM 100 operate synchronously with the clock signal CLK. A command which is defined by the row address strobe signal RAS, the column address strobe signal CAS, the write enable signal WE, the chip selection signal CS and the clock enable signal CKE are decoded by the command decoder 101.
An output signal of the command decoder 101 is supplied to the column control circuit 102 and the row control circuit 103. The row control circuit 103 controls the row address buffer 104. The row address buffer 104 supplies the address signals A0-A15 to the row-decoder 105. The row-decoder 105 decodes the address signals A0-A15 and a row in the memory cell array 106 is selected by an output of the row-decoder 105. Then, data is read from or written to cells in the row of the memory cell array 106.
On the other hand, the column control circuit 102 controls the column address buffer 107. The column address buffer 107 supplies the address signals A0-A15 to the column-decoder 108. The column-decoder 108 decodes the address signals A0-A15, and sense amplifiers in the sense amplifier block 109 are selected by an output of the column-decoder 108. Then, data is read or written through the sense amplifiers in the sense amplifier block 109. The column control circuit 102 selects the read amplifier block 110 according to an output of the command decoder 101 when data is read from the memory cell array 106. The read data is supplied from the sense amplifier block 109 to the input/output circuit 112 through the read amplifier 110. Then, the data DQ is output from the input/output circuit 112. On the other hand, the column control circuit 102 selects the write amplifier block 111 according to the output of the command decoder 101 when the data DQ is written to the memory cell array 106. Then, the data DQ supplied to the input/output circuit 112 is transferred to the write amplifier 111, and is written to the cell in the memory cell array 106 through the sense amplifier block 109.
FIGS. 2A, 2B and 2C show an outline of a 256-Mbit SDRAM. More particularly, FIG. 2A shows the outline of a chip of the 256-Mbit SDRAM. The SDRAM 100 has four 64-Mbit blocks. One of the 64-Mbit blocks 201 has four banks Bank0 to Bank3. FIG. 2B shows a construction of one of the banks Bank0. The Bank0118 corresponds to the Bank0 in FIG. 1. The Bank0 is divided into sixteen blocks in a vertical direction and eight blocks in a horizontal direction. As a result, the Bank0 has 128 small blocks. The Bank0 has the 128 small blocks 202, sense amplifiers S/As, read/write amplifiers AMPs, main-row-decoders MW/Ds, sub-row-decoders SW/Ds and column-decoders C/Ds. The sense amplifiers S/As correspond to the sense amplifier block 109 shown in FIG. 1, the read/write amplifiers AMPs correspond to the read/write amplifier block 120, the main-row-decoders MW/Ds and the sub-row-decoders SW/Ds correspond to the row-decoder 105 and the column-decoders C/Ds correspond to the column-decoder 108.
One small block 202 has 128-kbit memory cells. The sub-row-decoders SW/Ds and the sense amplifiers S/As are placed around the small block 202. The column-decoder C/Ds is placed on the top of each column and the sense amplifiers S/As is placed at the bottom of each column. Each row has one main-row-decoder MW/Ds. FIG. 2C shows a construction of one row of the Bank0. A power supply line 210 for core is placed parallel to the row. A column selection line 115 from the column-decoder C/Ds and a data bus 121 are placed perpendicularly to the row. Therefore, the column selection line 115 and the data bus 121 are placed in a direction parallel to the column.
However, the prior art described above has a drawback.
FIG. 3A shows a layout of conventional column selection lines CLA, CLB and FIG. 3B shows a data bus line 121, and a signal on the data bus line 121 when data is read from the memory cell block 106. The column selection lines CLA and CLB shown in FIG. 3A correspond to two column selection lines CLA and CLB shown in FIG. 2C. The data bus line 121 shown in FIG. 3A corresponds to the data bus line 121 which is placed parallel to the column selection lines CLA and CLB shown in FIG. 2C. The column selection line CLA is coupled to the data bus line 121 through a coupling capacitor 310 having a capacitance Cp. The data bus line 121 is coupled to a ground through a capacitor 311 having a capacitance Cdb. In case of a low integration degree DRAM, the capacitance Cp of the coupling capacitor 310 is low because a distance between the column selection line CLA and the data bus line 121 parallel to it is long. Therefore, a signal on the column selection line CLA does not affect the data bus line 121. However, recently, the distance between the column selection line CLA and the data bus line 121 is short because of a fine process to achieve a large scale integration and a multi-bit structure to achieve a wide band width of DRAMs. As a result, the capacitance Cp of the coupling capacitor 310 between the column selection line CLA and the data bus line 121 becomes high, so that the signal on the column selection line CLA affects the data bus line 121. Especially, a cross-talk due to the coupling capacitor 310 causes a problem because a signal amplitude on the data bus line 121 is too low so as to achieve a high speed operation and low power consumption.
FIG. 3B shows a signal 301 on the column selection line CLB, a signal 302 on the data bus 121 and an activation signal 303 for the read/write amplifier AMPs when the signal on the column selection line CLB does not affect the data bus line 121 because the capacitance Cp of the coupling capacitor 310 is low. FIG. 3C shows a signal 304 on the column selection line CLA, a signal 302 on the data bus 121 and an activation signal 303 for the read/write amplifier AMPs when the signal on the column selection line CLA affects the data bus line 121 because the capacitance Cp of the coupling capacitor 310 is high. In FIG. 3B, when the signal 301 on the column selection line CLB rises, the signal 302 on the data bus line 121 starts to decrease. When the value of the signal 302 decreases by Vdb, the activation signal 303 for the read/write amplifier AMPs rises and the read/write amplifier AMPs senses the signal 302 on the data bus line 121.
On the other hand, in FIG. 3C. a voltage variation Vp caused by a cross-talk due to the coupling capacitor 310 occurs. The voltage variation Vp on the data bus line 121 from the column selection line CLA is, EQU Vp=Cp.times.Vcl/(Cdb+Cp)
where Vcl is a voltage amplitude of the signal 304 on the column selection line CLA. Therefore, when the signal 304 on the column selection line CLA rises, the signal 302 on the data bus line 121 increases by Vp. Then, the signal 304 on the data bus line 121 decreases at the same rate as that of the signal 302 on the data bus line 121 shown in FIG. 3B. As a result, the activation signal 303 for the read/write amplifier AMPs needs to be activated after the signal 302 on the data bus line 121 decreases by Vdb+Vp. Therefore, a time interval between a rise point of the signal 304 and a rise point of the signal 303 in FIG. 3C is longer than a time interval between a rise point of the signal 301 and a rise point of the signal 303 in FIG. 3B.
Furthermore, the signal 302 may not reach the voltage Vdb by a point of time if the voltage Vp is very high. This causes a mis-detection of the data on the data bus line 121 by the read/write amplifier AMPs. When the voltage Vp is high, it is required to delay the activation of the read/write amplifier AMPs. Therefore, the coupling capacitance 310 of the coupling capacitor existing between the column selection line CLA and the data bus line 121 which is placed parallel to the column selection line CLA decreases an operation speed of the data bus line 121. This occurs when the data is read from the memory cell 106 and when the data is written to the memory cell 106.